1. Field of the Invention
The disclosed embodiments of the present invention relate to a dithering technique, and more particularly, to a method for performing dithering upon both the normal mode and the self refresh mode in a lower transmission data rate and related apparatus thereof .
2. Description of the Prior Art
Generally, a panel related processor or controller may use a dithering circuit for reducing the bandwidth and the buffer size therein, while still preventing the distortion from being easily noticed by human eyes in normal situations. However, the prior art is still imperfect and encounters dilemmas in many situations. For instance, please refer to FIG. 1, which is a diagram illustrating a conventional display processing system 100. The design of the display processing system 100 keeps the image quality for both the normal mode and the self refresh mode by disposing a dithering module 128 in the last stage of the whole circuit. In other words, both the 10-bit normal frames and the 10-bit self refresh frames coming from the preceding circuits are inputted into the dithering module 128, and then are outputted as an 8-bit dithering frame. One drawback of this kind of conservative design is the data path keeps being 10-bit for each channel till the end of the whole circuit (before the dithering module 128), and the frame buffer 124 is also for 10-bit frame size.
For another instance, please refer to FIG. 2, which is another diagram illustrating a conventional display processing system 200. The design of the display processing system 200 solves the problems encountered in the above mentioned architecture by disposing a dithering module 214 before the timing controller (TCON) 220. However, the processing system 200 keeps the image quality only for the normal mode. In other words, the last frame of the dithering frames is directly outputted to the display including the distortion induced by the 10-bit to 8-bit process in the dithering module 214.